Method of manufacturing an electronic device

ABSTRACT

In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 61/184,239, filed on Jun. 4, 2009, and entitled“Method of Manufacturing an Electronic Device,” which application isincorporated herein by reference.

TECHNICAL FIELD

This invention relates to MEMS (microelectromechanical systems)structures and methods of forming same, and more particularly to amethod of forming a deep trench in a semiconductor substrate andstructures resulting from same.

BACKGROUND

MEMS devices are becoming increasingly prevalent as new and additionalapplications are developed employing MEMS technology. In manyapplications, it is important that the manufacturing process for formingthe MEMS structure is compatible with integrated circuit manufacturingprocesses, particularly CMOS (complimentary metal-oxide-semiconductor)manufacturing processes. This is particularly so as, in manyapplications, MEMS devices are formed simultaneously with formation ofCMOS devices, or at least formed on the substrate as CMOS devices.

As CMOS technology develops, such as the push toward low k and extremelow k (ELK) dielectrics, new manufacturing processes must be developedto optimize the compatibility between the CMOS manufacturing steps andthe commensurate MEMS manufacturing processes.

SUMMARY OF THE INVENTION

In a first aspect, the present invention provides for a method ofmanufacturing an electronic device comprising forming an electroniccomponent on a substrate, and forming an interconnection layer above theelectronic component, the interconnection layer including at least onedielectric layer. The method further includes forming an opening in theinterconnection layer and exposing a portion of the substrate, anddepositing a film along a sidewall of the opening and on the substrate.The method also includes forming an opening in the film to expose aportion of the substrate, forming a deep trench in the substrate, andremoving at least part of the film.

In another aspect, the present invention provides for an electronicdevice comprising a substrate, and a plurality of dielectric layers onthe substrate. At least one of the plurality of dielectric layers has aconductive interconnect embedded therein. The electronic device furtherincludes an opening in the plurality of dielectric layers extending froma top dielectric layer through to the substrate, and a deep trench inthe substrate, the deep trench being in communication with, that is opento, the opening. The electronic device also includes a dielectricsidewall spacer on a sidewall of the opening in the plurality ofdielectric layers.

In yet another aspect, the present invention provides for an electronicsystem. The electronic device system includes a first device and asecond device. The first device comprises a substrate, interconnectionlayers formed atop the substrate and including at least one low-kdielectric layer, an opening formed in the interconnection layers andopen to a trench formed within the substrate, and a dielectric filmformed along a sidewall of the opening.

The second device comprises a second substrate, second interconnectionlayers formed atop the substrate and including at least one second low-kdielectric layer, a second opening formed in the second interconnectionlayers and communicating with a second trench formed within the secondsubstrate, and a second dielectric film formed along a sidewall of thesecond opening. The first and second devices are aligned such that thefirst opening and second opening and the first trench and second trenchare aligned. The electronic system also includes a spacer extending fromwithin the first trench to within the second trench.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an exemplary device in which electronic devices, suchas CMOS devices, are manufactured on a common substrate with MEMSdevices;

FIGS. 2 a through 2 g illustrate various stages in the manufacture of anillustrative embodiment electronic device employing aspects of thepresent invention; and

FIG. 3 illustrates an exemplary electronic system employing aspects ofthe present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the illustrative embodiments are discussed indetail below. It should be appreciated, however, that the presentinvention provides many applicable inventive concepts that can beembodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

FIG. 1 illustrates an exemplary device 1 in which electronic devices,such as CMOS devices, are manufactured on a common substrate with MEMSdevices. Device 1 is shown in an intermediate stage of manufacture.Exemplary device 1 includes a substrate 2 upon and in which are formedvarious electronic components 4 (e.g., PMOS transistors, NMOStransistors, capacitors, resistors, and the like). The variouselectronic components are interconnected and connected to othercomponents external to device 1 through multiple layers ofinterconnections 6. In an illustrative embodiment, interconnections 6are one or more conductive layers formed within one or more dielectriclayers. For example, each such conductive layer could be a copperconductor embedded within an inter-metal dielectric (IMD) layer, formedusing well known damascene processes. As is also known, the top mostconductive layer could include bond pads (for connection to externaldevices) and a passivation formed thereover. For simplicity, conductivelayers, IMD layers, bond pad layers, passivation layers are collectivelyreferred to as interconnections 6 in FIG. 1.

Opening 8 is also illustrated in FIG. 1. Opening 8 includes an opening10 formed within interconnections layers 6 and a deep trench 12 formedwithin substrate 2. Opening 8 could be employed as part of a MEMSdevice, could be employed for mechanically aligning and interconnectingtwo separate devices 1, or other application. Regardless of theapplication, it is often desirable to control the angle Φ of thesidewall of deep trench 12. It is also generally desirable to form deeptrench 12 quickly from a manufacturing efficiency perspective.

In an exemplary manufacturing process, substrate 2 is a siliconsubstrate and deep trench 12 is formed by a wet etching process usingTMAH (Tetramethylammonium hydroxide) etchant. Typically, TMAH etchesthrough silicon substrate 2 at roughly 0.8μ/min under standard etchprocessing parameters. It has been noted, however, that when low-kdielectrics, such as carbon doped silicon oxide (frequently referred toas Black Diamond, available from Applied Materials, Santa Clara,Calif.), fluorine doped silicon glass (FSG), porous low-k films, and thelike are employed in interconnection layers 6, the presence of theselow-k dielectric layers may significantly reduce the etch rate ofsilicon substrate 2. Low-k is a term of art that generally refers to adielectric having a dielectric constant less than that of silicon oxide,i.e., less than about 3.9. In some instances, it has been noted that theetch rate degrades from about 0.8μ/min in the presence of conventionaldielectrics (e.g., FSG) to about 0.022μ/min in the presence of low-kdielectrics. Because deep trench 12 may be as much as 1-1000μ deep, thisdegradation of etching rate can significantly increase manufacturingtime and hence the overall manufacturing costs of device 1.

Another adverse consequence that may result from the manufacture ofopening 8 is that the opening 10 formed within interconnections layer 6is formed using standard photolithography processes, including thedeposition, patterning, and subsequent removal of one or morephotoresist layers (not shown) on device 1. Because deep trench 12 isdesirably relatively deep with a relatively narrow mouth, residualphotoresist material may remain in the bottom of deep trench 12 despiteefforts to remove all photoresist material from device 1. This canadversely impact subsequent manufacturing steps and can materiallyaffect the performance of device 1.

FIG. 2 a illustrates device 1 in an earlier stage of manufacture(relative to FIG. 1). As shown in FIG. 2 a, electronic components 4 havebeen formed in and on substrate 2 using known processes, such as knownCMOS manufacturing techniques. Interconnections layers 6 have beenformed over electronic components, such as through known dual-damasceneor single damascene process in which conductive wires and vias areformed within respective low-k dielectric layers. Bond layer andpassivation layers are also formed and patterned using conventionaltechniques. At the stage of manufacture illustrated in FIG. 2 a, theCMOS components of device 1 are effectively complete.

FIG. 2 b illustrates a subsequent step in the formation of opening 8. Asillustrated, a photoresist layer 14 is formed and patterned atop device1. Using patterned photoresist layer 14 as a mask, opening 10 is formedwithin (i.e., through) interconnections layers 6. In an illustrativeembodiment, opening 10 is formed by a dry etch process such as exposureto, e.g., CF₄, CHF₃, and the like, in an appropriate etch chamber.

After opening 10 is formed, photoresist layer 14 is removed, such as bya conventional ashing technique, also referred to as an oxide plasmaremoval. Note that because photoresist layer 14 is removed prior to theformation of deep trench 12, the risk of residual photoresist materialremaining at the bottom of deep trench 12 is eliminated.

In order to protect the IMD dielectric layers, which in the illustratedembodiments are ELK dielectrics, a sidewall protection film 16 isformed, as illustrated in FIG. 2 c. In an illustrative embodiment,sidewall protection film is a composite film of an oxide layer 16 a anda nitride layer 16 b. Oxide layer 16 a may be formed using conventionalchemical vapor deposition (CVD) techniques and deposited to a thicknessof from about one to about twenty microns. One skilled in the art willrecognize that other deposition techniques, such as TEOS, high pressureCVD (HPVCD), and the like could alternatively be employed to form oxidelayer 16 a. In various embodiments, oxide layer 16 a acts as a bufferlayer between the dielectric layers of interconnections layers 6 andnitride layer 16 b to reduce or eliminate stress that would otherwisearise at the interface between the dielectric layers and nitride layer16 b. This eliminates or reduces the risk of damage to or delaminationof the dielectric layers.

Nitride layer 16 b may also be formed using a convention CVD depositionprocess, or plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), orother known deposition technique. Nitride layer 16 b may be deposited toa thickness of from about one to about twenty microns. Nitride layer 16b is a silicon nitride in the illustrated example and provides theadvantageous feature of high etch selectivity relative to substrate 2,as will be described further below. In other embodiments, SiON, SiCN,SiC, or other materials and combinations of materials could be used fornitride layer 16 b, as could other materials provided they providesufficient etch selectivity relative substrate 2.

A second photoresist layer 18 is next formed over device 1, asillustrated in FIG. 2 d. Using conventional photolithography processes,photoresist layer 18 is patterned to expose sidewall protection film 16at the bottom of opening 10. This portion of sidewall protection film 16is removed in order to expose and then etch substrate 2 to form deeptrench 12, as described more fully below. Using a conventional dryetching process, such as a passivation dry etch, the nitride layer iffirst removed (e.g., using a first etch recipe and process) and then theunderlying oxide is removed (e.g., using a second etch recipe andprocess that is tuned to the oxide layer). FIG. 2 e illustrates device 1after photoresist layer 18 has been removed, such as by an oxide plasmaor ashing process. At this stage, sidewall protection film 16 remains onthe sidewalls of opening 10 and also remains on those portions ofsubstrate 2 at the bottom of opening 10 that were previously covered byphotoresist layer 18. In this example, sidewall protection film 16 alsoacts as a hard mask for defining the dimensions of (subsequently formed)deep trench 12.

FIG. 2 f illustrates device 1 after deep trench 12 has been formed insubstrate 2. In the illustrated embodiment, deep trench 12 is formed bya wet etch process using TMAH. In an exemplary embodiment, device 1 isdipped into a solution of TMAH having a concentration of from about 1%to about 35% at a temperature of from about 30 C to about 100 C. Oneskilled in the art will recognize that a wet TMAH etch is an isotropicetch and hence sidewalls of deep trench 12 will be formed with an angleΦ relative to a major surface of substrate 2. The value of angle Φ canbe controlled by adjusting the concentration of TMAH, the temperature ofthe solution, and the duration of the etch process. An angle Φ of fromabout 40° to about 65° may be advantageous for several applications. Invarious embodiments such an angle can be readily obtained by adjustingthe above described parameters. Likewise, in some embodiments, acritical dimension CD, as illustrated in FIG. 2 f, could be readilyobtained using the above described etch process. Note that the presenceof sidewall protection film 16 during the wet etch process shouldadvantageously reduce or eliminate damage to or delamination ofdielectric layers in interconnections layers 6. Note further that deeptrench 12 is in communication with opening 10, meaning they are open toeach other.

As illustrated in FIG. 2 g, sidewall protection film can besubstantially removed after formation of deep trench 12. In someembodiments, sidewall protection film 16 could be completely removed. Inthe illustrated embodiment, however, sidewall protection film 16 isremoved using an anisotropic etching technique which removes the filmfrom horizontal surfaces (such as atop interconnections layers 6 and thetop surface of substrate 2), while leaving the film intact on verticalsurfaces (such as the sidewalls of opening 10). Techniques foranisotropically removing an oxide, a nitride, or a compositeoxide/nitride film are well known in the art in order to achieveso-called sidewall spacers such as are commonly formed on CMOStransistor gates. As one skilled in the art will readily appreciate,those teachings can be applied to etching sidewall protection film 16 inorder to form sidewall spacers 20 as shown in FIG. 2 g. Two advantagesmay be realized by leaving sidewall spacers 20 intact. First, there issubstantial risk of damaging the dielectric layers of interconnectionslayers 6 associated with removing sidewall protection film from thesidewalls of opening 10. Recall that sidewall protection film 16 mayinclude an underlying oxide layer 16 a; removing this oxide layer raisesa significant risk of inadvertently etching back or otherwise damagingthe material of the dielectric layers of interconnections layers 6.Leaving sidewall protection film 16 intact on the sidewalls reduces thisrisk. Second, by leaving sidewall spacers 20 may also serve to protectdielectric layers of interconnections layers 6 during subsequentprocessing, and may, in fact, provide structure support to thedielectric layers as well.

FIG. 3 illustrates an application employing two devices 1 a and 1 bhaving been manufactured as described above. In the illustratedapplication devices 1 a and 1 b are electrically interconnect usingcapacitive coupling through signal pads 22 a on device 1 a andcorresponding signal pads 22 b on device 1 b. In order for effectivecapacitive coupling of the devices, an air gap 24 in various embodimentsis carefully maintained. As shown, spacer ball 26 is one way to maintainan appropriate spacing or air gap between devices. A first opening 8 ais formed in device 1 a using the above described techniques and acorresponding opening 8 b is formed in device 1 b also using the abovedescribed techniques. Spacer ball 26 is formed or deposited within firstopening 8 a. When device 1 a and 1 b are brought into alignment with oneanother, spacer ball 26 fits within both opening 8 a and opening 8 b,and extends above and beyond each opening 8 a and 8 b. By carefulcontrol of the CD and the depth of opening 8 a and 8 b and the diameterof spacer ball 26, precise control of the air gap 24 between devices 1 aand 1 b can be obtained and maintained.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. For example,many of the features and process steps discussed above can beimplemented using conventional CMOS processes or using othersemiconductor manufacturing processes.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. An electronic device comprising: a substrate; aplurality of dielectric layers on the substrate, at least one of theplurality of dielectric layers having a conductive interconnect embeddedtherein; an opening in the plurality of dielectric layers extending froma top dielectric layer through to the substrate; a deep trench in thesubstrate, the deep trench being open to the opening; and a dielectricsidewall spacer only on a sidewall of the opening in the plurality ofdielectric layers.
 2. The electronic device of claim 1 wherein thedielectric sidewall spacer comprises a nitride layer overlying an oxidelayer.
 3. The electronic device of claim 1 wherein at least one of theplurality of dielectric layers comprises a low-k dielectric layer. 4.The electronic device of claim 1 further comprising a spacer balllocated within the deep trench and extending above and beyond the deeptrench.
 5. The electronic device of claim 1 wherein the dielectricsidewall spacer comprises at least one material selected from the groupconsisting essentially of SiN, SiON, SiC, and SiCN, and SiO2.
 6. Theelectronic device of claim 1 wherein the deep trench has a sidewallhaving an angle of between 40 and 65 degrees, relative to a major topsurface of the substrate.
 7. The electronic device of claim 1 whereinthe substrate comprises silicon.
 8. The electronic device of claim 1further comprising a signal pad atop the plurality of dielectric layers.9. The electronic device of claim 1, further comprising: a secondsubstrate; a second plurality of dielectric layers on the secondsubstrate, at least one of the second plurality of dielectric layershaving a second conductive interconnect embedded therein; a secondopening in the second plurality of dielectric layers extending from asecond top dielectric layer through to the second substrate; a seconddeep trench in the second substrate, the second deep trench being opento the second opening; a second dielectric sidewall spacer only on asecond sidewall of the second opening in the second plurality ofdielectric layers; the substrate and the second substrate being alignedsuch that the opening and the second trench are aligned; and a spacerextending from within the deep trench to within the second deep trench.10. The electronic device of claim 9 further comprising a signal pad onthe substrate and a corresponding second signal pad on the secondsubstrate.
 11. The electronic device of claim 10 wherein the signal padand corresponding second signal pad are capacitively coupled.
 12. Theelectronic device of claim 9 wherein the opening and the second openinghave respective diameters of between about 10μ and about 1,000μ.
 13. Theelectronic system of claim 9 wherein the trench and the second trenchinclude respective sidewalls having an angle of between about 40 andabout 65 degrees relative to a major top surface of the respectivesubstrate and the second substrate.